The second, 21164 or EV5, was the first microprocessor to place a large secondary cache on chip.

In most 3D games (except Unreal) the lack of secondary cache makes almost no difference.

The Alpha 21264 has two levels of cache, a primary cache and secondary cache.

The process shrink enabled both cores and a secondary cache to be contained on a die.

Without a secondary cache, a chip may take longer to transmit information, so early reviews of the Celeron were poor.

Intel intends to introduce more Celerons this year, including chips with a secondary cache.

Chip frequency and size of secondary cache on the box in between are currently undecided.

The usually power-hungry secondary cache uses an access method which only switches on the portion being accessed.

Some of this information is associated with instructions, in both the level 1 instruction cache and the unified secondary cache.

The K8 uses an interesting trick to store prediction information with instructions in the secondary cache.