To render that at 30 frame/s requires an extremely fast memory bus.

All ranks are connected to the same memory bus (address+data).

Integrated circuit packages may have a limit on the number of pins available to provide the memory bus.

The next major change to the core is with its memory bus.

The R300 was the first board to truly take advantage of a 256-bit memory bus.

The internal memory bus to the cache, for instance, was 128 bits wide.

Access to this memory bus had to be prioritized, as well.

Higher code density means less data movement on the memory bus, improving performance.

In another second or two, the beam may severe my primary memory bus.

Systems could include up to 32 processors with up to 512 shared memory buses.