Since only a few packages are chip size, the meaning of the acronym was adapted to chip-scale packaging.

The company said the technology reduced chip size and allowed it to couple many central processing units together.

The ever-shrinking chip size causes the heat to concentrate within a small area and leads to high power density.

Figures of merit for single-chip packaging techniques are chip size, hermeticity, and processing temperature.

They are very expensive to produce, using techniques similar to microprocessor construction but with "chip" sizes on the scale of several centimeters.

Right now, the company is upping its capacity by both increasing the chip size and increasing the density of reactions on the chip.

Using embedded memory improves performance but also takes up space, forcing either an increase in chip size, which lowers yields, or a decrease in performance.

This would be done by removing non-essential features to reduce the chip size.

Smaller process geometries can be used (therefore reducing chip size and cost)

Manufacturers have to balance the need to minimize the chip size against additional functionality.