MIPS instruction set

However, the use of the MIPS instruction set allowed them to correct many of their compatibility issues.

They instead invested more time in their compiler's register allocation, making sure it wisely used the larger set available in the MIPS instruction set.

This was to avoid giving the impression that the emulator was confined to the MIPS instruction set, which was the only architecture being emulated initially.

These instructions are accepted by the MIPS assembler, although they are not real instructions within the MIPS instruction set.

Subsequent NonStop Guardian machines using the MIPS instruction set were known to programmers as TNS/R machines, but had a variety of marketing names.

The decode stage ended up with quite a lot of hardware: the MIPS instruction set had the possibility of branching if two registers were equal, so a 32-bit-wide AND tree ran in series after the register file read, making a very long critical path through this stage.